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alex100's avatar
alex100
Icon for New Contributor rankNew Contributor
2 years ago

Error (16021) using 10M08SCE144C8G

I'm utilizing the MAX10 FPGA, specifically the 10M08SCE144C8G model, to generate sweeping sinewave signals using lookup tables and multipliers. However, during compilation, I encountered the followin...
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NurAiman_M_Intel's avatar
NurAiman_M_Intel
Icon for Super Contributor rankSuper Contributor
2 years ago

Hi,


  1. What is the setting when compiling those 2 devices? Is there any differences? (Compilation setting)
  2. Please also share the compilation report for 10M016SCE144C8G.
  3. Can you share your design in .qar?


Regards,

Aiman


  • alex100's avatar
    alex100
    Icon for New Contributor rankNew Contributor
    2 years ago


    Hi NurAiman,

    1. I'm a bit uncertain about what you're referring to with '(Compilation Setting)'. The only alteration I made was within the 'Device and Pin Option' where I set the Configuration to 'Single Uncompressed Image (256Kbits UFM)' for both chips.

    2. This is the flow Summary (using 10M16SCE144C8G) after compiling:


    "-----------------------------------
    Flow Status Successful - Wed Feb 21 09:48:40 2024
    Quartus Prime Version 21.1.1 Build 850 06/23/2022 SJ Lite Edition
    Revision Name Ramp50M
    Top-level Entity Name Ramp50M
    Family MAX 10
    Device 10M16SCE144C8G
    Timing Models Final
    Total logic elements 7,786 / 15,840 ( 49 % )
    Total registers 1088
    Total pins 32 / 101 ( 32 % )
    Total virtual pins 0
    Total memory bits 0 / 562,176 ( 0 % )
    Embedded Multiplier 9-bit elements 90 / 90 ( 100 % )
    Total PLLs 0 / 1 ( 0 % )
    UFM blocks 0 / 1 ( 0 % )
    ADC blocks 0

    -----------------------------------"

    3. I'm unsure about creating a .qar file. Could you guide me through the steps to make one?