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alex100's avatar
alex100
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2 years ago

Error (16021) using 10M08SCE144C8G

I'm utilizing the MAX10 FPGA, specifically the 10M08SCE144C8G model, to generate sweeping sinewave signals using lookup tables and multipliers. However, during compilation, I encountered the followin...
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NurAiman_M_Intel's avatar
NurAiman_M_Intel
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2 years ago

Hi,


The workaround are using VHDL. You can just convert it to verilog.


Regards,

Aiman


alex100's avatar
alex100
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2 years ago


Hi FvM and NurAiman_M_Intel,

I appreciate your answers. My Verilog design includes a lookup table with 4096 addresses, and I need to store numbers associated with each address. It appears that the lookup table is the root cause of the issue.

Two challenges have left me puzzled:

1. It appears that the 10M0xSCE chip lacks flash memory, making it unable to store numeric data like a Lookup Table (LUT) or vector initialization. However, I understand that its logic cells can be utilized as a form of memory. Could you confirm if my understanding is correct?

2. As I showed earlier I successfully compiled the design using the 10M16SCE144C8G chip, with the output indicating "Total logic elements 7,807 / 15,840 ( 49 % )". However, when attempting to compile the same design using the 10M08SCE144C8G chip, it indicates "Total logic elements 11,504 / 8,064 ( 143 % )". I'm curious as to why more logic elements are needed in the latter case and would appreciate any insights you may have.