Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd

Hi tiny007,

I also think it is a library issue. I have generated it in Verilog but I have the same problem.

The weird thing is that I have also generated it on another laptop and it works. The only difference is that in the last one I have installed the 30-day evaluation Quartus II and in the other one the Quartus II web-edition.

Do you have other idea for solving the problem?

Thank you.

Hi nic_@,

Actually it is the opposite: the web edition gives the error and the 30-day evaluation Quartus II is ok.

Maybe the problem is that with the web edition you don't have some libraries.

I have to check if I can copy the library files from the one that works to the other one.

Anyway, thank you for your reply.

Hi nic_@,

Actually it is the opposite: the web-edition gives the error and the 30-day evaluation no.

Maybe it is a problem of licence, with the web-edition you cannot use the embedded ADC. Someone of you know if this is the problem?

Thank you.

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Hi all,

I am trying to use the embedded ADC in Max10 (10M08SAE144C8GES). I have generated the Altera Modular ADC IP Core, the ALTPLL IP Core and the JTAG to Avalon Master Bridge, as suggested in "MAX10 Analog to Digital Converter User Guide". However, when I synthesize the module I obtain these errors:

Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(7): design library "altera_sld" does not contain primary unit "sld_hub_pack"

Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(7): selected name in use clause is not an expanded name

Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(8): design library "altera_sld" does not contain primary unit "sld_jtag_hub_pack"

Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(8): selected name in use clause is not an expanded name

Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(9): design library "altera_sld" does not contain primary unit "jtag_pack"

Error (10800): VHDL error at alt_sld_fab_alt_sld_fab_sldfabric.vhd(9): selected name in use clause is not an expanded name

This file vhd is automatically generated by Quartus 15.0 software. I think it is a problem of library. Does someone know how fix this problem?

Thank you for your help.

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I ran into this exact same problem and found out why it occurred for me. Perhaps it will help you.

My Quartus environment for version 15 is on Windows 10 running under Parallels VM on a Mac. I was running lab 3 from the DECA workshop course put on by Arrow. This lab creates a NIOS II processor and shows off the QSYS, Quartus, and Eclipse tools. All the files were on my Mac desktop and to make the lab easier to find in the file dialogs, I mapped the folder to a drive letter. The first time I compiled I did not see this error but because I had made a naming error in QSYS, I had to go back and rename a module. From then on, I got this error. What eventually cleared the error was to map a drive letter to a folder higher up in the directory structure:

So instead of L:\labfolder

I did: M:folder1\folder2\labfolder

This seemed to fix the problem. I don't know if it will help you in your case but it solved it for me and perhaps there is a bug being exposed by the method I used.

Interestingly, 40% of the workshop attendants were using Macs to run Quartus. Not sure if this is saying Mac people would like to develop hardware or hardware people like to use Macs.

I suspect, that this Error (10481) happens in Quartus 15.0 and 15.1.

Does anyone knows how to solve this issue?