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Altera_Forum
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10 years ago

Error (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd

Hi all, I am trying to use the embedded ADC in Max10 (10M08SAE144C8GES). I have generated the Altera Modular ADC IP Core, the ALTPLL IP Core and the JTAG to Avalon Master Bridge, as suggested in "...
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Altera_Forum
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10 years ago

Hi tiny007,

I also think it is a library issue. I have generated it in Verilog but I have the same problem.

The weird thing is that I have also generated it on another laptop and it works. The only difference is that in the last one I have installed the 30-day evaluation Quartus II and in the other one the Quartus II web-edition.

Do you have other idea for solving the problem?

Thank you.