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Altera_Forum
Honored Contributor
Honored ContributorError (10481): VHDL Use Clause error at alt_sld_fab_alt_sld_fab_sldfabric.vhd
Hi all, I am trying to use the embedded ADC in Max10 (10M08SAE144C8GES). I have generated the Altera Modular ADC IP Core, the ALTPLL IP Core and the JTAG to Avalon Master Bridge, as suggested in "...
Altera_ForumHonored Contributor
Honored ContributorSeems like some libraries are missing. If you try to generate in Verilog, will similar missing library issue occur?
