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Altera_Forum
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17 years ago

EP3S150ES VCC/VCCL Resistance to ground

Hi All:

We just got a board back, and we are seeing an oddity on the 1.1V supply.

We haven't powered the board yet, because of this.

Right now we are seeing ~3-4 Ohm resistance to ground on the 1.1V supply (VCCL/VCC) of the EP3S150ES device.

The rest of the supplies look good with between ~15 to ~160 ohms depending on the supply.

Our black boards all look good, and but the board we put a mechanical sample on also shows this ~4 ohms to ground for the 1.1 supply, even though no other compononents are stuffed.

Any Ideas??

Thanks

Pete

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    we are seeing ~3-4 Ohm resistance to ground on the 1.1V supply

    --- Quote End ---

    That's normal for core voltage of FPGA.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks.. I have it powered. But so far no joy on configuration. Both JTAG and AS fail.

    JTAG is flaky right now, some times it scans, but most the time it doesn't. If it scans, It then tries to program and says config done failed to go high.

    Any ideas?

    So far all the supplies are up and ok, and I've double/triple checked the pull-ups/downs in the configuration area.
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    Thanks.. I have it powered. But so far no joy on configuration. Both JTAG and AS fail.

    JTAG is flaky right now, some times it scans, but most the time it doesn't. If it scans, It then tries to program and says config done failed to go high.

    Any ideas?

    So far all the supplies are up and ok, and I've double/triple checked the pull-ups/downs in the configuration area.

    --- Quote End ---

    Hello, i have the same issue with Stratix 3 FPGA (EP3SL150fF1152C4N). Resistance at uninstalled and unprogrammed FPGA between Vccl 1.1V and GND is about 2 Ohms, but i am afraid to power it on, because Stratix 3 is expensive for me. Did you resolve this problem? Does this mean that chip is defective?
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    VCCINT resistance of just a couple of OHMs are normal for larger FPGA's.

    To be extra safe, validate your blank board ohms out ok for this supply, then compare to the resistance of a working dev board with a similar part (if you have one)

    If you supply is sized correctly it should power up.

    For the JTAG issue I was experiencing we had a couple of issues.

    One the wrong VCC was connected to the JTAG port, causing reliability issues.

    Two the JTAG clock had some transmission line issues, due to the cable assembly required, that was solved by increasing the source termination inside the USB-Blaster from 10 ohm to 33 ohms.

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    --- Quote Start ---

    VCCINT resistance of just a couple of OHMs are normal for larger FPGA's.

    To be extra safe, validate your blank board ohms out ok for this supply, then compare to the resistance of a working dev board with a similar part (if you have one)

    If you supply is sized correctly it should power up.

    For the JTAG issue I was experiencing we had a couple of issues.

    One the wrong VCC was connected to the JTAG port, causing reliability issues.

    Two the JTAG clock had some transmission line issues, due to the cable assembly required, that was solved by increasing the source termination inside the USB-Blaster from 10 ohm to 33 ohms.

    Pete

    --- Quote End ---

    Thank you. I have powered the board on. Power supply on board works correct, but Quartus can't detect an FPGA yet))
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hello) We connected all configuration pins (nSTATUS, CONF_DONE, nCONFIG, nCE, nCEO, MSEL[2:0], DATA0, DCLK, nCSO, ASDO) as described at figure 11–12 in Stratix III handbook for Fast Active Serial programming. In the same time we connect pins for JTAG (TCK, TDO, TMS, TDI, TRST) as described at figure 11-19. VCCPGM and VCCPD are connected to the same pin 3.3 V. Also we connect each pin (nCSO, DCLK, DATA0, ASDO) through capacitor (10 pF) to GND. JTAG configuration doesn't work (quartus can't detect device). During active serial programming Quartus loads configuration data to memory chip (EPCS64 SI16M) successfully (program/configure, verify, blanck check), but FPGA does not work after programming. It also doesn't work after power supply reset. I attached a basic picture which shows the scheme of connection (without capacitors).https://www.alteraforum.com/forum/attachment.php?attachmentid=8445

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Are you sure all power supplies to the FPGA are up? There are several that will keep the device in power on reset. if they are not up all the way.

    there's also a note on the ramp time of VCCPD and VCCPGM:

    --- Quote Start ---

    VCCPGM and VCCPD must ramp up from 0 V to the desired voltage level within 100 ms. If

    these supplies are not ramped up within this specified time, your Stratix III device

    will not configure successfully. If your system does not allow ramp-up time of 100 ms

    or less, you must hold nCONFIG low until all power supplies are stable.

    --- Quote End ---

    When you are trying to configure it via active serial, are you seeing any activity on the DCLK, DATA0 and CS pins?

    Pete
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hello) All power supplies to the FPGA are up but DC/DC converter used to generate 1.1V for Stratix III is hot (it is about 40-70 degrees Centigrade). 3.3V and 1.1V power supplies are ramped up within 100 ms (about 15 ms) as you can see at attached picture ("Rump_up"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8466 I am seeing activity on the DCLK, DATA0 and CS pins, When we are trying to configure it via active serial (picture "AS_PROG_SUCCESSFUL"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8467 I must note that I don't see any activity at pin TDO during JTAG programming (picture "TEST_JTAG_CHAIN_FAIL_3"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8468 I also attached a picture that shows programmer connections scheme. https://www.alteraforum.com/forum/attachment.php?attachmentid=8469

    Regards,

    Alex.