EP3S150ES VCC/VCCL Resistance to ground

Hello) All power supplies to the FPGA are up but DC/DC converter used to generate 1.1V for Stratix III is hot (it is about 40-70 degrees Centigrade). 3.3V and 1.1V power supplies are ramped up within 100 ms (about 15 ms) as you can see at attached picture ("Rump_up"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8466 I am seeing activity on the DCLK, DATA0 and CS pins, When we are trying to configure it via active serial (picture "AS_PROG_SUCCESSFUL"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8467 I must note that I don't see any activity at pin TDO during JTAG programming (picture "TEST_JTAG_CHAIN_FAIL_3"). https://www.alteraforum.com/forum/attachment.php?attachmentid=8468 I also attached a picture that shows programmer connections scheme. https://www.alteraforum.com/forum/attachment.php?attachmentid=8469