EP3S150ES VCC/VCCL Resistance to ground

Hello) We connected all configuration pins (nSTATUS, CONF_DONE, nCONFIG, nCE, nCEO, MSEL[2:0], DATA0, DCLK, nCSO, ASDO) as described at figure 11–12 in Stratix III handbook for Fast Active Serial programming. In the same time we connect pins for JTAG (TCK, TDO, TMS, TDI, TRST) as described at figure 11-19. VCCPGM and VCCPD are connected to the same pin 3.3 V. Also we connect each pin (nCSO, DCLK, DATA0, ASDO) through capacitor (10 pF) to GND. JTAG configuration doesn't work (quartus can't detect device). During active serial programming Quartus loads configuration data to memory chip (EPCS64 SI16M) successfully (program/configure, verify, blanck check), but FPGA does not work after programming. It also doesn't work after power supply reset. I attached a basic picture which shows the scheme of connection (without capacitors).https://www.alteraforum.com/forum/attachment.php?attachmentid=8445