Efficient 16-bit std_logic_vector comparator in VHDL

The issue I'm facing is that after synthesis, the comparator uses a significant amount of resources (image below) specifically, it uses 2 CARRY4 blocks and too much LUTs. My professor, who assigned this task, explicitly stated that I must not convert a and b to integer, unsigned, or any other numeric type. They must be compared as std_logic_vector.

Is there a way to implement a more resource-efficient comparator under these constraints? Any ideas or patterns to reduce the number of LUTs or avoid the use of carry chains would be appreciated.

Here is the code :

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity comparator is
    Port (
        clk, rst : in std_logic;
        a, b     : in std_logic_vector (15 downto 0);
        max, min : out std_logic_vector (15 downto 0)
    );
end comparator;

architecture Behavioral of comparator is

signal max_int, min_int : std_logic_vector (15 downto 0);
begin

process (clk)
begin   
    if (rst = '1') then
    
        min_int <= (others => '0');
        max_int <= (others => '0');
       
    elsif (rising_edge(clk)) then
    
        if (a <= b) then
            min_int <= a;
            max_int <= b;
        else
            min_int <= b;
            max_int <= a;
        end if;
        
    end if;

Thanks in advance!