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Kuru's avatar
Kuru
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8 months ago

Efficient 16-bit std_logic_vector comparator in VHDL

I'm working on a VHDL project where I need to implement a comparator between two 16-bit std_logic_vector signals, a and b. The goal is to check if a is greater than, less than, or equal to b. Th...
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FvM's avatar
FvM
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8 months ago
Using different numerical types has no effect on resource consumption, arithmetic operation is essentially the same.

Using carry chain is appropriate for fast comparator, Quartus selects it automatically as default implementation.

Most LUT are used for 32 mux output bits and have nothing to do with comparator function as such.
  • Kuru's avatar
    Kuru
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    8 months ago

    So, are there no alternatives? Is this the best solution?
    Do you think I could write the VHDL code in a way that uses even fewer resources?

  • FvM's avatar
    FvM
    Icon for Super Contributor rankSuper Contributor
    8 months ago
    Forgot to mention, to perform numeric operations with std_logic_vector, you need to add VHDL2008 numeric_unsigned or numeric_signed library. Or non-standard Synopsis library before VHDL2008.