Downloading ELF Process failed of Project

Yes you need to define your timing requirements.

For the on-chip memory the only thing you need to define is your clock input frequency and use the derive_pll_clocks command. Timequest will determine all the internal timing from this.

For the SDRAM and Flash you need to define the I/O timing.

Dear Daixiwen

so I need return "SOPC Builder"

and set pll of three output :

system_clk(100Mhz)

sdram_clk(100Mhz -65deg)

onchip_clk(100Mhz -130deg) <-- for on-chip(Enth &#9472; DMA use) clk

your mean is this ?

And I still don't understand your mean of defin the i/o timing ...

can you explanation this mean of defin : ) ?

No, both your clocks and IO timing must be defined in Timequest. Have a look at this user guide (http://www.alterawiki.com/wiki/timequest_user_guide).

Why are you using a 130 degres phase on the onchip clock? This will create unnecessary timing constraints on the design. Just use the same clock for your system and the on chip ram.

Dear Daixiwen

The 130 degrees set is myself speculate and try use...

M...the User Guide I will read , if I have new found or progress

I will immediately return : )

Dear Daixiwen

I do it of near , because I found

At assignments of setting , in the Timequest Timing Analyzer .

Need add "project_name.sdc" file , the file include Enth_Rx_Clk

and clk50 setting .

But I have new questin ....when I download success ,

The NiosII bsp tell me :

InterNiche Portable TCP/IP , V3.1

Copyright 1996-2008 by InterNiche Technologies. All right reserved.

prep_tse_mac 0

your Enthnet Mac address is 00:07:ed:ff:e2:d7

prepped 1 interface , initializing ...

[tse_mac_init]

INFO : TSE MAC 0 found at address 0x05002000

error : mac group[0] - no phy connected!

error : no phy connected! speed = 100 , duplex = full

ok , x=0 , CMD_CONFIG=0x00000000

MAC post-initialization : CMD_CONFIG=0x04000203

[tse_sgdma_read_init] RX descriptor chain desc (1 depth) created

mctest init called

IP addres of et1 : 0.0.0.0

Created "Inet main" task (Prio : 2)

Created "clock tick" task (Prio : 3)

I think ... It is my hardware problem ?

But when I connected to Internet cable

My Internet chip of indicate led is normal...

(ENET_LED_LINK100&#12289;ENET_LED_DUPLEX&#12289;ENET_LED_RX)

The no PHY connected message means that something is wrong with the MDIO signals - either the clock or the data. Check that you connected them correctly, especially the bidirectionnal data signal, as you have 3 signals to/from the TSE that you need to combine in a single tristate buffer.

It should still work, as long as the Ethernet connection is using the same speed the TSE is configured to. Without the MDIO communication the TSE has no way of finding out what speed the PHY negotiated on the link.

Dear Daixiwen

I check the Enet_rx_clk_pll component , it is one input three output ,

one input :

ENET0_RX_CLK - 125MHZ from Internet Chip

three output (All 125MHZ) :

enet_rx_clk_270 0° deg to Nios Process input "rx_clk_to_the_tse_mac"

enet_tx_clk_mac 90° deg to Nios Process input "tx_clk_to_the_tse_mac"

enet_tx_clk_phy 180° deg to ddr_o component input "outlock"

(ddr_o is ALTDDIO_OUT , three input , one output of link ENET0_GTX_CLK)

---------------------------------------------------------------

And about ENET0_MDIO config (Verilog file) :

assign NET0_mdio_in = ENET0_MDIO;

assign ENET0_MDIO = NET0_mdio_oen ? 1'bz : NET0_mdio_out;

NET0_mdio_in : link to Nios process intput mdio_in_to_the_tse_mac

NET0_mdio_oen : from Nios Process output mdio_oen_from_the_tse_mac

NET0_mdio_out : from Nios Process output mdio_out_from_the_tse_mac

---------------------------------------------------------------

and Nios II Windows have new message

info : phy[0.0] - checking link...

info : phy[0.0] - link established

warning : phy[0.0] - phy not found in phy profile

info : phy[0.0] - speed = 100 , duplex = full

ok , x=0 , cmd_config=0x00000000

Why are you using those phase shifts on the clock? Just use the same one everywhere.

What PHY chip do you have? Is it one that is included in the TSE driver?

Dear Daixiwen

About phase shifts on the clock , I reference the de2_115_web_server

of QuartusII config , so I use the enet_rx_clk_pll component.

And my Internet chip is use 88e1111 , and my QuartusII Core is copy

example of web_server_de2_115 , but my core is use CyclonII . at my

hardware indicate led have rx&#12289;duplex&#12289;link1000 .

But link1000 should not be bright...it is abnormal...

should be bright is link100...

(Refer DE2-115 Board , it bright RX&#12289;DUPLEX&#12289;LINk100&#12289;TX(have cable))

TSE driver ? your mean is QuartusII on the setting &#8594; files and add altera

Built-in ip code ? I have do of add that .

(altera &#8594; triple_speed_ethernet &#8594; lib &#8594; ip code)

I think...maybe problem is from my QuartusII Project...or hardware problem

just I think ... and I will keep try : )

I'm not familliar with the de2-115 kit examples. I've used the Cyclone III developper board, which uses only one clock for the Ethernet connection and it works fine.

By driver I meant the C driver. The PHY chips drivers are in altera\xxx\ip\altera\triple_speed_ethernet\lib\sopc_builder\altera_triple_speed_ethernet\HAL\src\altera_avalon_tse.c

The 88e1111 is a supported PHY chip so you shouldn't see the text "PHY not found in PHY profile". This means you still have a problem with the MDIO communication. Maybe using a scope or Signaltap on the clock and data lines will help you find out what's wrong.

It looks like the PHY chip negotiated a 1Gb/s but the driver doesn't now that (as it can't communicate with the PHY) and switch by default to a 100Mb/s speed.