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Altera_Forum
Honored Contributor
Honored ContributorDownloading ELF Process failed of Project
Good night everybody , I have problem of QuartusII 10.1sp1 . My user chip is CycloneII EP2C35FC8 , when my sopc builder use Pll、SDRAM、FLASH、MCU、JTAG , I can run...
Altera_ForumHonored Contributor
Honored ContributorNo, both your clocks and IO timing must be defined in Timequest. Have a look at this user guide (http://www.alterawiki.com/wiki/timequest_user_guide).
Why are you using a 130 degres phase on the onchip clock? This will create unnecessary timing constraints on the design. Just use the same clock for your system and the on chip ram.
