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Altera_Forum
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13 years ago

Downloading ELF Process failed of Project

Good night everybody , I have problem of QuartusII 10.1sp1 . My user chip is CycloneII EP2C35FC8 , when my sopc builder use Pll、SDRAM、FLASH、MCU、JTAG , I can run...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Yes you need to define your timing requirements.

For the on-chip memory the only thing you need to define is your clock input frequency and use the derive_pll_clocks command. Timequest will determine all the internal timing from this.

For the SDRAM and Flash you need to define the I/O timing.