Don't optimize away method issue need your help

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"Warning: LATCH primitive "inst37" is permanently enabled"

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Yes, the warning says just what you have written in your code. It's a warning, not an error.

You didn't tell, what's in the "gatedl" block. But I guess, it's a logic cell delay chain, that is simply ignored by the compiler. Right?

Did you read my post in your previous same-topic thread? The CPLD synthesis tool doesn't support "keeping" of redundant logic cells, even by synthesis attributes.

Hi FvM:

Thanks!

But i run below code in my design, and can be implemented very well. And this code just is the block "Gatedly":

---------code start-----------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

library altera;

use altera.altera_syn_attributes.all;

ENTITY Gatedly IS

generic(

DELAY : positive :=9

);

PORT (

trig_in : in std_logic;

trig_out : out std_logic

);

END Gatedly;

ARCHITECTURE arch OF Gatedly IS

signal delay_line: std_logic_vector(DELAY-1 downto 0);

attribute keep: boolean;

attribute keep of delay_line: signal is true;

BEGIN

gen_delay:

for i IN 1 TO DELAY-1 generate

delay_line(i) <= delay_line(i-1);

end generate;

delay_line(0) <= trig_in;

trig_out <= delay_line(DELAY-1);

END arch;

------code end-----------------

And i can get attached tpd values when change the "DELAY" value for each trigger signal.

In fact, my quesiton is how to use the rest 512 registers resource?

And my terminal goal is to get the longest tpd value for each signal input CPLD. You know I just need more delay time for these input signals.

Seems like you found a way to keep CPLD macro cells. I'll study the results later on.

Regarding registers, you should refer to the MAX7000 macro cell description in the datasheet. There's no dedicated latch available, just a DFF with a bypass path. So, if you don't need a synchronous register, it's simply bypassed. I don't see, how it could work as a delay element.

Can you post a minimal design, where the gatedly block is instantiated and actually consumes macrocells? Or are you using additional global settings?

P.S.: I found that "Ignores LCELL buffers" must be set to "off". Because the synthesis attribute in gatedly doesn't work alone. Both have to be set.

Hi FvM,

Thanks for your kindly reply!

I am unconnectly these days, and sorry for the delay of this reply.

I attach my project, and i found "ignore lcell" setting is not activity for my project or CPLD devices. When i set off or auto, the result is same.

I found beow your reply in another thread:

"However, regarding achieved delay, I don't see additional options to increase it, except for routing the signal in and out of I/O pins. You should also consider, that you don't necessarily increase the delay by using a slower speed grade. The specification is about maximum delay, these devices are designed as logic chips rather than delay lines."

Do you mean that I don't need to trust the tpd report? If will these tpd information change after implemented into CPLD device?