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Altera_Forum
Honored Contributor
16 years agoDon't optimize away method issue need your help
Hi all: I am using EPM7512AETC144-12 device. There many trigger signals need to be delayed in my design. For the limitation of the resource, i use gate delay to archive this function. I ...
Altera_Forum
Honored Contributor
16 years agoCan you post a minimal design, where the gatedly block is instantiated and actually consumes macrocells? Or are you using additional global settings?
P.S.: I found that "Ignores LCELL buffers" must be set to "off". Because the synthesis attribute in gatedly doesn't work alone. Both have to be set.