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Altera_Forum
Honored Contributor
16 years agoDon't optimize away method issue need your help
Hi all: I am using EPM7512AETC144-12 device. There many trigger signals need to be delayed in my design. For the limitation of the resource, i use gate delay to archive this function. I ...
Altera_Forum
Honored Contributor
16 years agoHi FvM,
Thanks for your kindly reply! I am unconnectly these days, and sorry for the delay of this reply. I attach my project, and i found "ignore lcell" setting is not activity for my project or CPLD devices. When i set off or auto, the result is same. I found beow your reply in another thread: "However, regarding achieved delay, I don't see additional options to increase it, except for routing the signal in and out of I/O pins. You should also consider, that you don't necessarily increase the delay by using a slower speed grade. The specification is about maximum delay, these devices are designed as logic chips rather than delay lines." Do you mean that I don't need to trust the tpd report? If will these tpd information change after implemented into CPLD device?