Don't optimize away method issue need your help

Hi FvM:

Thanks!

But i run below code in my design, and can be implemented very well. And this code just is the block "Gatedly":

---------code start-----------------

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

use IEEE.std_logic_arith.all;

use IEEE.std_logic_unsigned.all;

library altera;

use altera.altera_syn_attributes.all;

ENTITY Gatedly IS

generic(

DELAY : positive :=9

);

PORT (

trig_in : in std_logic;

trig_out : out std_logic

);

END Gatedly;

ARCHITECTURE arch OF Gatedly IS

signal delay_line: std_logic_vector(DELAY-1 downto 0);

attribute keep: boolean;

attribute keep of delay_line: signal is true;

BEGIN

gen_delay:

for i IN 1 TO DELAY-1 generate

delay_line(i) <= delay_line(i-1);

end generate;

delay_line(0) <= trig_in;

trig_out <= delay_line(DELAY-1);

END arch;

------code end-----------------

And i can get attached tpd values when change the "DELAY" value for each trigger signal.