Do you use LPMs for your LFSRs?

Apologies for some confusion I caused about the two forms of lfsr. There are two equivalent types(Fibonacci and Galois). I was thinking only of Fibonacci type with taps feeding back onto first stage.

Thanks to all. I had made a stupid mistake, I had 'clock' in my process but I was actually using a different (reduced) clock in my simulation. Once I corrected that it worked perfectly. I have read up quite a lot on LFSRs so it was really bugging me!:rolleyes: Thanks again. This forum is invaluable.

process(reset,clock)
begin
if reset = '1' then
   shift_reg <= "0001"; -- seed
elsif rising_edge(clock) then
   shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps
   shift_reg(2) <= shift_reg(1); -- shift
   shift_reg(3) <= shift_reg(2);
end if;
output    <=    shift_reg;
end process;

according to xilinx doc a 4 bit shift register should have taps at 3,4

Your feedback point should be stage 0 not stage 1

By using the simulator within Quartus, I just ran the simulator, expecting to see 'output' change value each clock cycle but it is a constant value of '1'. It seems that the output sticks at whatever value I set the seed to be, i.e. a seed of 1111 resuts in a constant output of 15.

It looks like a correct implementation of x^4 + x^3 + 1. How did you test it?

I changed the code to reflect a 4-bit LFSR that I know should step through all possible combinations, i.e. maximal length.

process(reset,clock)
begin
if reset = '1' then
   shift_reg <= "0001"; -- seed
elsif rising_edge(clock) then
   shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps
   shift_reg(2) <= shift_reg(1); -- shift
   shift_reg(3) <= shift_reg(2);
   shift_reg(0) <= shift_reg(3);
   
end if;
output    <=    shift_reg;
end process;

Probably your xor results in 1 always.