Forum Discussion
Altera_Forum
Honored Contributor
15 years agoI changed the code to reflect a 4-bit LFSR that I know should step through all possible combinations, i.e. maximal length.
process(reset,clock)
begin
if reset = '1' then
shift_reg <= "0001"; -- seed
elsif rising_edge(clock) then
shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps
shift_reg(2) <= shift_reg(1); -- shift
shift_reg(3) <= shift_reg(2);
shift_reg(0) <= shift_reg(3);
end if;
output <= shift_reg;
end process; It still does not seem to work though.