Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- Thanks again Kaz. I can't quite see where I was going wrong
process(reset,clock)
begin
if reset = '1' then
shift_reg <= "0001"; -- seed
elsif rising_edge(clock) then
shift_reg(1) <= shift_reg(0) XOR shift_reg(3); -- taps
shift_reg(2) <= shift_reg(1); -- shift
shift_reg(3) <= shift_reg(2);
end if;
output <= shift_reg;
end process;When I simulate this the output is always 1? --- Quote End --- This is a perfect implementation of 4-bits LFSR. If it stays at 1, check your reset signal. Good luck, Ton