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Altera_Forum
Honored Contributor
15 years agoaccording to xilinx doc a 4 bit shift register should have taps at 3,4
shift_reg(0) <= shift_reg(2) xor shift_reg(3); shift_reg(3 downto 1) <= shift_reg(2 downro 0);according to xilinx doc a 4 bit shift register should have taps at 3,4
shift_reg(0) <= shift_reg(2) xor shift_reg(3); shift_reg(3 downto 1) <= shift_reg(2 downro 0);