Forum Discussion
Altera_Forum
Honored Contributor
15 years ago --- Quote Start --- It seems that the output sticks at whatever value I set the seed to be, i.e. a seed of 1111 resuts in a constant output of 15. --- Quote End --- The design is showing a perfect LFSR sequence of length 15 in simulation. I guess you missed to release the reset signal - or supplied no clock. --- Quote Start --- according to xilinx doc a 4 bit shift register should have taps at 3,4 --- Quote End --- This is a different form of the same sequence.