Honored ContributorI want to add a SignalTap module I generated with the MegaWizard to my design. Does the SignalTap module have to be instantiated at the top level of the design or can I instantiate it in a lower level module?
Honored ContributorThere is a SignalTap megafunction which needs to be instantiated, but everyone uses the File -> New -> SignalTap II. This file does not need to be instantiated at all, and is added under Assignments -> Settings -> SignalTap II. It is a much easier flow, allows for quick adding/removing of .stp files, and allows the user to tap nodes without manually hooking it up. There are reasons for the megafunction, but everyone uses the .stp files due to its many benefits.
Honored ContributorThanks for your comments, but we are using the SignalTap modules generated by the MegaWizard so I still need know whether the SignalTap modules generated by the MegaWizard have to be instantiated at the top level of the design. Thanks again.
Honored ContributorNaturally it could be instantiated anywhere since hierarchy doesn't mean anything in the fitter, but you might have to bring signals to the top-level to get them out JTAG. Looking at the megafunction though, the only signals are the inputs of what you're tapping and clock. So the JTAG connection must be back-doored just like with an .stp file. So no, there wouldn't be any reason to put it at the top-level or signals to bring to the top-level. Out of curiousity, how come you're using the megafunction?
Honored Contributorthe reason is that signaltapii adds it's own registers to the project, closer to my registers that need to be tapped. this consumes space on chip planner,forcing my project to stretch in all directions.and this of course creates additional timing issues. so i want to give a logic lock to the signal tap, exactly where i want it to be.that's why we are going for megafunctions.second reason why i'm trying to do that is that whenever i create partitions for my modules,compiler understands that similar module elements must be packed together. this forces stii registers to be thrown further away; after which stii is not able to tap signals correctly. so this is the second reason why i want to direct stii where "to be or not to be" :) .
Honored ContributorUsually adding a SignalTap doesn't hurt timing, since the connection to your logic is just a single register to register interface. I've seen lots of designs add the SignalTap to an already place-and-routed design(compile your design normally, set Top partition to Post-Fit, then add SignalTap and refit).
Also, SignalTap added through the GUI still ends up being a hierarchy in the design, so you can still assign it to a LogicLock region if you really want to. Finally, the fitter is not driven by partitions. They are all stitched together in the partition merge stage, and the fitter places them like they were a flat netlist(unless some are post-fit). So creating partitions won't direct the fitter to put stuff closer together. (Your timing assignments and design connectivity will drive them closer together). Partitions will stop unnecessary logic from being thrown away, as it stops synthesis at the boundary level. You can change this behavior, but sounds like it's what you want. Technically that is good for the design since it's unnecessary, but it may preserve something that is interesting for you to tap with SignalTap. I've used the noprune synthesis attribute to do this before(open your HDL in Quartus and go to Edit -> Insert Template -> VHDL/Verilog -> Synthesis Attributes -> No Prune) It sounds like what you're doing is working, and that's the main thing, just throwing out some other ideas. Good luck.Honored Contributor1. a agree, if using post fitting netlist that solves alot,it freezes already compiled project and adds stii around the project labs. but that needs 2 compilations. one for your modules and next for post fitting, handbook tells us that post fitting netlists should take smaller amount of time since no synthesis is performed,however to me that method reduced 10seconds compilation time only.i suspect that's because of my HDD. the data exchange between hard drive and CPU takes lot of time, i should try it with SSD.
2.SignalTap added through the GUI does ends up being a hierarchy in the design, but before adding logic lock, i must create signaltap partition, and when i try to do that to the GUI created signaltap instance, here is what i get "Can't set a partition on "sld_signaltap:auto_signaltap_0"because it is a megafunction instantiation " :( 3. yes you are totally correct about partition merge stage. and about stopping unnecessary logic from being thrown away at the boundary level, as i remember this option was called something like "inter partition optimizations". guess it gets disabled automatically when we create partitions, noprune attribute and virtual pin are my devoted friends :) 4.Rysc, i always wondered, are you working at altera? i mean, all the answerer guys under the nickname status "Altera Guru " are altera's forum support stuff or ordinary guys from all over the world?Honored Contributor4. I work for Altera, although answering the forum isn't a responsibility of mine, just something I try to help out with. (You'll see I seldom answer more than what's off the top of my head). That being said, I believe a lot of the other Gurus are ordinary engineers. Or should I say extraordinary :)
Honored ContributorIt seems that the original question was never answered - because I have the same question, and find no answer here.
I have instantiated a SignalTap-II in one of my modules. Every thing seems OK, except the "SignalTap II Logic Analyzer" can not find it. The two messages I have to choose from are "Invalid SOF" and "JTAG Communication Error" Neither error is enlightening, and of all the documentation read, this post is the closest to an answer. (And as I noticed, it doesn't answer). Any clues? How do I get the Logic Analyzer (sp) to see the instantiated SignalTap? It shows up in the hierarchy and all that, I just can't connect to it. And to turn off any "why don't you do it the silly hard way with the buggy GUI?" questions, yes, there is a reason why I want/need to instantiate the SignalTap megafunction in user code.Honored Contributorbefore compiling make sure you go to quartus -> tools menu ->signal tap logic analyzer. click it, from popup window choose signals you want to tap. save it. then go to quartus -> assignments menu -> settings -> signaltap logic analyzer submenu -> and click enable signal tap logic analyzer checkbox and choose your saved stp file from the browse button click ok. compile. after compilation go to quartus -> tools menu ->signal tap logic analyzer on the right top corner there are buttons. choose your prgrammer there (usb programmer or something) and your device should get detected.if programmer is not found mess with the programmer cable or the driver. if programmer gets detected and fpga does not, click scan chain.if it does not find the fpga anyway then the fpga is not powered up. if it does finds the fpga, choose compilation generated sof file from browse button and click program. if it says invalid sof file make sure your fpga model in quartus matches to the real fpga model on the circuitboard (this ep4c83275752c something thing) the rest will be obvious by itself.
Honored ContributorMany responses, but no answer. The last response doesn't seem to have anything to so with the original question: "do SignalTap modules have to be instantiated at the top level of a design?"
I have instantiated a SignalTap-II module, verified that it is consuming resources, and it shows it in the hierarchy viewer. I have gotten past the "Invalid SOF" and "JTAG Communication Error" messages - there was a question there that never got answered. And the SignalTap-II analyzer still can't find it. It will let me add a second one, and connect to the signals that were going into the first one (what signals weren't optimized away), but it will not let me look at an RTL-Instantiated SignalTap. I want to be able to instantiate a SignalTap and actually use it. How does one do that? (I viewed the tutorial and the only mention of instantiating a SignalTap in RTL was: "It can be done, but we are not going to show you how".)
