do SignalTap modules have to be instantiated at the top level of a design

before compiling make sure you go to quartus -> tools menu ->signal tap logic analyzer. click it, from popup window choose signals you want to tap. save it. then go to quartus -> assignments menu -> settings -> signaltap logic analyzer submenu -> and click enable signal tap logic analyzer checkbox and choose your saved stp file from the browse button click ok. compile. after compilation go to quartus -> tools menu ->signal tap logic analyzer on the right top corner there are buttons. choose your prgrammer there (usb programmer or something) and your device should get detected.if programmer is not found mess with the programmer cable or the driver. if programmer gets detected and fpga does not, click scan chain.if it does not find the fpga anyway then the fpga is not powered up. if it does finds the fpga, choose compilation generated sof file from browse button and click program. if it says invalid sof file make sure your fpga model in quartus matches to the real fpga model on the circuitboard (this ep4c83275752c something thing) the rest will be obvious by itself.