do SignalTap modules have to be instantiated at the top level of a design

the reason is that signaltapii adds it's own registers to the project, closer to my registers that need to be tapped. this consumes space on chip planner,forcing my project to stretch in all directions.and this of course creates additional timing issues. so i want to give a logic lock to the signal tap, exactly where i want it to be.that's why we are going for megafunctions.second reason why i'm trying to do that is that whenever i create partitions for my modules,compiler understands that similar module elements must be packed together. this forces stii registers to be thrown further away; after which stii is not able to tap signals correctly. so this is the second reason why i want to direct stii where "to be or not to be" :) .