do SignalTap modules have to be instantiated at the top level of a design

Usually adding a SignalTap doesn't hurt timing, since the connection to your logic is just a single register to register interface. I've seen lots of designs add the SignalTap to an already place-and-routed design(compile your design normally, set Top partition to Post-Fit, then add SignalTap and refit).

Also, SignalTap added through the GUI still ends up being a hierarchy in the design, so you can still assign it to a LogicLock region if you really want to.

Finally, the fitter is not driven by partitions. They are all stitched together in the partition merge stage, and the fitter places them like they were a flat netlist(unless some are post-fit). So creating partitions won't direct the fitter to put stuff closer together. (Your timing assignments and design connectivity will drive them closer together).

Partitions will stop unnecessary logic from being thrown away, as it stops synthesis at the boundary level. You can change this behavior, but sounds like it's what you want. Technically that is good for the design since it's unnecessary, but it may preserve something that is interesting for you to tap with SignalTap. I've used the noprune synthesis attribute to do this before(open your HDL in Quartus and go to Edit -> Insert Template -> VHDL/Verilog -> Synthesis Attributes -> No Prune)

It sounds like what you're doing is working, and that's the main thing, just throwing out some other ideas. Good luck.