do SignalTap modules have to be instantiated at the top level of a design

1. a agree, if using post fitting netlist that solves alot,it freezes already compiled project and adds stii around the project labs. but that needs 2 compilations. one for your modules and next for post fitting, handbook tells us that post fitting netlists should take smaller amount of time since no synthesis is performed,however to me that method reduced 10seconds compilation time only.i suspect that's because of my HDD. the data exchange between hard drive and CPU takes lot of time, i should try it with SSD.

2.SignalTap added through the GUI does ends up being a hierarchy in the design, but before adding logic lock, i must create signaltap partition, and when i try to do that to the GUI created signaltap instance, here is what i get "Can't set a partition on "sld_signaltap:auto_signaltap_0"because it is a megafunction instantiation " :(

3. yes you are totally correct about partition merge stage. and about stopping unnecessary logic from being thrown away at the boundary level, as i remember this option was called something like "inter partition optimizations". guess it gets disabled automatically when we create partitions, noprune attribute and virtual pin are my devoted friends :)

4.Rysc, i always wondered, are you working at altera? i mean, all the answerer guys under the nickname status "Altera Guru " are altera's forum support stuff or ordinary guys from all over the world?