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Altera_Forum's avatar
Altera_Forum
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14 years ago

Dividing clock source - PLL

Hello,

I was trying to reduce clock frequency of Cyclone II i Quartus form 50MHz to 5 Hz. I heard, this need to be done by megawizard, SoPC builder and then PLL. But the thing is, that I cannot smaller the frequency to less than 10MHz. I've searched many web pages to find the solution, and I'vo got no. Could anyone give me a simple step by step answer how to reduce the clock frequency, or just give some clues?

Regards,

blasq

5 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    5 Hz is much too slow for a PLL, and as you can see, the minimum output of a PLL is 10MHz.

    What you need to do is clock your 5Hz logic at 50MHz, and generate a clock enable that makes the circuit appear to run at 5Hz.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for reply, @Tricky

    I don't see it clear. Let's suppose I have one LED pin out, and I want to supply it with 5Hz pulse. I create a PLL with enable input? And then, how to connect it?

    thanks for help,

    blasq
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    For led use a counter running from 0 to 10,000,000-1 and connect The counter msb to the led.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Ok, I got it. But how can I do such a big counter? I don't see arbitral-value counter in symbols or SoPC builder.

    thanks,

    blasq
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    24 bit counter will do. just do it in HDL yourself.

    The pulse generated wouldn't be 50%duty cycle.

    if you want 50%duty cycle use a bit of logic on your counter to set led high/low equally, high from 0 to 5,000,000-1 then low