Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorDividing clock source - PLL
Hello, I was trying to reduce clock frequency of Cyclone II i Quartus form 50MHz to 5 Hz. I heard, this need to be done by megawizard, SoPC builder and then PLL. But the thing is, that I canno...
Altera_ForumHonored Contributor
Honored Contributor24 bit counter will do. just do it in HDL yourself.
The pulse generated wouldn't be 50%duty cycle. if you want 50%duty cycle use a bit of logic on your counter to set led high/low equally, high from 0 to 5,000,000-1 then low
