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Honored Contributor
Honored ContributorDividing clock source - PLL
Hello, I was trying to reduce clock frequency of Cyclone II i Quartus form 50MHz to 5 Hz. I heard, this need to be done by megawizard, SoPC builder and then PLL. But the thing is, that I canno...
Altera_ForumHonored Contributor
Honored ContributorOk, I got it. But how can I do such a big counter? I don't see arbitral-value counter in symbols or SoPC builder.
thanks, blasq
