Delay line withine Cyclone3 device

Hi Folks,

I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:

    BEGIN
    
    IF (rising_edge(CLK)) THEN
        temp_sign_in <= INPUT;
    
    END IF;
    
    temp_sign_4 <= temp_sign_in AND (NOT SHORT_DELAY) AND (NOT LONG_DELAY);
        
    temp_sign_1 <= temp_sign_in;
        
    temp_sign_5 <= temp_sign_1 AND SHORT_DELAY;
        
    temp_sign_2 <= temp_sign_1;
        
    temp_sign_6 <= temp_sign_2 AND LONG_DELAY;
        
    OUTPUT <= NOT (temp_sign_4 OR temp_sign_5 OR temp_sign_6);
    
    END PROCESS;

At first, the input signal will be reclocked, and after that the signal is forked into 3 AND-branches, that will all have an increased delay. In the end, the signal will be joined by an OR-gate to the output. To prevent the Altera Sythesis to delete those redundant traces, I decleared the signals as follows:

--- Quote Start ---

SIGNAL temp_sign_in: std_logic;

SIGNAL temp_sign_1: std_logic;

SIGNAL temp_sign_2: std_logic;

SIGNAL temp_sign_3: std_logic;

SIGNAL temp_sign_4: std_logic;

SIGNAL temp_sign_5: std_logic;

SIGNAL temp_sign_6: std_logic;

attribute syn_keep: boolean;

attribute syn_keep of temp_sign_in: signal is true;

attribute syn_keep of temp_sign_1: signal is true;

attribute syn_keep of temp_sign_2: signal is true;

attribute syn_keep of temp_sign_3: signal is true;

attribute syn_keep of temp_sign_4: signal is true;

attribute syn_keep of temp_sign_5: signal is true;

attribute syn_keep of temp_sign_6: signal is true;

--- Quote End ---

Actually this works quite fine, all the signals are kept as I can see form the Technology Map Viewer. Unfortunately, the Synthesis adds some logic inbetween the delay registers (actually this logic lies in the overlying VHDL-code, so I guess the sythesis wants to save space). What I don't want.

I tried to use the LogicLock-Option on my VHDL-File. In the Chip Planner the Cells aren't moved, but it doesn't prevent the Synthesis to alter my LUTs.

Now my question: Is there another way what I can do to protect the structure I want to have?

Thank you for any comment!