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Honored Contributor
Honored ContributorDelay line withine Cyclone3 device
Hi Folks, I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:
BEGIN
IF (rising_edge(CLK)) THEN
temp_sign_...
Altera_ForumHonored Contributor
Honored Contributori would try incremental compile and maybe an imported post-fit .qxp file. create a new project with your delay HDL, fit it, and export as a post-fit netlist. you could even put it in a logic lock. then import the .qxp into your top level project and preserve fit information, it shouldn't try to reoptimize
i'd be interested in the results if you try it
