Delay line withine Cyclone3 device

Dear pancake, thank you for your hint. I have implemented it in the way you mentioned. Now the Synthesis and the Fitter are leaving this part of the FPGA untouched. Thanks for your advice!

@ Tricky: I actually don't want to align signals. Since there are some HF-signals on my board (32 times the clock frequency of the FPGA), for some frequency-bands the setup/hold times of some D-latches aren't kept. To prevent this, I am inserting an additional delay. Everything works fine now. Sorry for my VHDL coding style, i'm relatively new to FPGAs.