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Honored Contributor
Honored ContributorDelay line withine Cyclone3 device
Hi Folks, I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:
BEGIN
IF (rising_edge(CLK)) THEN
temp_sign_...
Altera_ForumHonored Contributor
Honored ContributorI just want to ask why? trying to align signals like this is never going to work reliably. secondly: why have you got all the combinatorial logic in a process?
