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Honored Contributor
Honored ContributorDelay line withine Cyclone3 device
Hi Folks, I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:
BEGIN
IF (rising_edge(CLK)) THEN
temp_sign_...
Altera_ForumHonored Contributor
Honored ContributorIm still concerned that you are trying to manually fudge something. The problem with fudging delays is that while they may work at room temp, as the board heats up or cools the delay can change, so you then violate your setup and hold times again, and it's going to happen without much warning and could easily be intermittent.
