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Honored Contributor
Honored ContributorDelay line withine Cyclone3 device
Hi Folks, I want to implement a delay line in my Cyclone 3 FPGA. Therefore I wrote the following a process in VHDL file:
BEGIN
IF (rising_edge(CLK)) THEN
temp_sign_...
Altera_ForumHonored Contributor
Honored ContributorThank you Tricky for telling me your concerns.
You are right, my delay line settings are only valid when the board is at a specific temperature. However, I don't consider this as a problem.
