DDR3, time quest & afi_half_clk freq.

If you are using the memory controller IP, timing constraints are created for you automatically. You shouldn't have to change anything other than constraints for your own internal design. Which device are you using and are you sure you selected half-rate mode in the controller's IP Parameter Editor?

Thanks.

Hi,

I agree with your comment, and the FPGA works in this way. The problem is in reference to time quests analysis; it considers 1/4 clock.

You see in Time Quest what you should see. As I said afi_half_clk depends on controller rate (Afi ratio). If you configured your controler as a Half-rate and 350MHz, then your afi_half_clk = 350/4 and Time Quest should report afi_half_clk = 87.5. If you want clock that is half of the interface use afi_clk not afi_half_clk.

I forgot to comment that, at the beginning, I tested the half_rate clock freq. using two counter; one with a 125MHz clock, and another with the half_rate clk.

I have just repeat the test. In this case, I have included 3 counters:

Can you post your Clock tree report of Time Quest? Have you correctly tracked source of the afi_half_clk?

Try to use different Quartus version. Maybe there is some bug in your current Quartus version

The problem is the order of the constraints file (SDC). The IP sdc file must be the last one.