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Altera_Forum
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9 years ago

DDR3, time quest & afi_half_clk freq.

I've a project with a DDR3L SDRAM controller (quartus 15.1) , using a afi_half_clk = 350/2Mhz for the avalon the interface. The project is working, and if a compare a counter with a 125MHz and the af...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Thanks.

I know that I don't have change the constreains files generated by the IP controller. It was just a way to ask for any idea/solution.

We are using the FPGA 5CGTFD9E5F31C7.

The IP controller is configured as enabled Hard ext. interface.

The Avalon interface is confured as Full-rate, and enabled the Half-rate clock.