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Altera_Forum
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9 years ago

DDR3, time quest & afi_half_clk freq.

I've a project with a DDR3L SDRAM controller (quartus 15.1) , using a afi_half_clk = 350/2Mhz for the avalon the interface. The project is working, and if a compare a counter with a 125MHz and the af...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

If you are using the memory controller IP, timing constraints are created for you automatically. You shouldn't have to change anything other than constraints for your own internal design. Which device are you using and are you sure you selected half-rate mode in the controller's IP Parameter Editor?