Altera_ForumHonored Contributor9 years agoDDR3, time quest & afi_half_clk freq. I've a project with a DDR3L SDRAM controller (quartus 15.1) , using a afi_half_clk = 350/2Mhz for the avalon the interface. The project is working, and if a compare a counter with a 125MHz and the af...Show More
Altera_ForumHonored Contributor9 years agoTry to use different Quartus version. Maybe there is some bug in your current Quartus version
Recent DiscussionsWorst-Case Completion Time for PLL Dynamic Phase Shift (PHASESTEP → PHASEDONE)Agilex5 - Timings configuration10M04SCU169I7G issue.HDMI example design errors with Agilex 7Agilex 7 DDR4 Reset and ADDR/CMD Clock PCB Implementation Documentation Discrepancy