Altera_ForumHonored Contributor9 years agoDDR3, time quest & afi_half_clk freq. I've a project with a DDR3L SDRAM controller (quartus 15.1) , using a afi_half_clk = 350/2Mhz for the avalon the interface. The project is working, and if a compare a counter with a 125MHz and the af...Show More
Altera_ForumHonored Contributor9 years agoTry to use different Quartus version. Maybe there is some bug in your current Quartus version
Recent DiscussionsError (209014): CONF_DONE pin failed to go high in device 1.Implementation of lower data rate.eFUSE : Agilex F series and AGilex I series PCIe cardIP components used in the design have conflicting settings. Intel PCIE Ftile MCDMAEP4CGX22CF19C8N Failure Short D8 to C8