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Altera_Forum's avatar
Altera_Forum
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13 years ago

DDR2 hard memory interface in ARRIA V

Hello,

Its the first time I'm using ddr2 hard memory for altera .

can somebody explain the hard memory ddr2 interface?

what signals should I drive in : AFI I/Os ? what do I need it for?

afi_clk

afi_half_clk

afi_reset_n

what signals should I drive in :calibration/command I/Os

mp_cmd_clk_0_clk

mp_cmd_reset_n_0_reset_n

mp_rfifo_clk_0_clk

mp_rfifo_reset_n_0_reset_n

mp_wfifo_clk_0_clk

mp_wfifo_reset_n_0_reset_n

local_init_done

local_cal_success

local_cal_fail

local_refresh_req

local_refresh_chip

local_refresh_ack

oct_rzqin

Many thanks

8 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Any name with the AFI_ is the Avalon Interface from Altera, you can view it as a generic bus. The width of the bus varies with the speed / width you are running on the DDR2/3 interface. All that is configured for you thru MegaWizard (I am using the soft-core instead so maybe there's some difference). I suggest running the complete example design (can be conveniently generated by open the project file, and run the <vhdl/verilog>.tcl script) to visually help understand how the bus works.

    Here are some links that maybe helpful to you:

    Section 9 – MegaWizard Plug-In Manager Flow of the following: http://www.altera.com/literature/hb/external-memory/emi_plan.pdf

    For an overview read this section: http://www.altera.com/literature/hb/external-memory/emi_intro.pdf

    There is also a Stratix III/IV UniPHY tutorial: http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf

    Here is all the documentation on the External Memory Interface Handbook: http://www.altera.com/literature/hb/external-memory/emi.pdf

    Hope this helps
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi,

    Many thanks for your help. I've created a ddr2 ip with megawizard. like you said, it generate an example "ddr2_example_design".

    I run the <vhdl/verilog>.tcl script , the project was compailed and I can see Waves.

    some of the signals are RED (unknown state) : init_done,cal_success,cal_fail,status_fail...

    in the model sim transcript window I see an error :ERROR: Invalid arc in, fsm:AVL_FSM, state:AVL_IDLE

    # Instance: ddr2_example_sim.e0.if0.p0.ddr2_example_sim_e0_if0_p0_ddr2_example_sim_e0_if0_p0_acv_hard_memphy_umemphy_arriav_mem_phy_hphy_inst_6080.inst.<protected>.<protected>

    # Time: 17867500

    # ERROR: Invalid arc in, fsm:AVL_FSM, state:AVL_IDLE

    # Instance: ddr2_example_sim.e0.if0.p0.ddr2_example_sim_e0_if0_p0_ddr2_example_sim_e0_if0_p0_acv_hard_memphy_umemphy_arriav_mem_phy_hphy_inst_6080.inst.<protected>.<protected>

    # Time: 17880000

    Do you know what is this error?

    Thanks
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    It sounds like it could not find the Altera and/or Arria V libraries. Or not all of the libraries are compiled. Try look into msim_setup.tcl to see if all the path to the Altera files are setup properly, if not, you could hard-code it to your exact path and run again.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi

    I fixed it, but now I have different problem. the ddr2_example_design simulation doesn't work well.

    I implemented a Hard memory interface (ddr2) for ARRIA V in the megawizard. And I wanted to activate the example design.

    I run ddr2_example_design example design exactly as described in README.txt file

    - open the Quartus project "generate_sim_example_design.qpf" and select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".The generated files will be found in the subdirectory "vhdl".

    - To simulate the example design using Modelsim AE/SE:

    1. Move into the directory ./verilog/mentor or ./vhdl/mentor

    2. Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

    In the Wave I don't see any action in the ddr2 signals(dq,dqs) its always in tri-state.

    Attached the Wave screenshot.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Can you try simulate longer to see when does the local_init_done is complete? For my simulation it took about 135500uS.

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    I am not sure about this but maybe someone could confirm.

    I was also having problems trying to get the Arria V Hard Memory Interface to work. Everything built and compiled OK and the timing looked reasonable but on the actual board the DDR would not calibrate and start up. I tried reducing the clock speed [was 400MHz] down to something far less critical but still no luck.

    Last September I was at a trade show where Altera had a booth so I went to see if anyone could help me. I was told that actually the HMI interface is not yet supported in Quartus for Arria V and wouldn't be until 12.2

    We have had parts now for more than 1 year [ES] but still I am confused as to whether or not we can use this function especially as it APPEARS to work in QSYS..... so far I have had little response direct from Altera.
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    hello,

    I have tried to run model sim for 135500uS , but my simulation is very slow. i am using model sim altera 12.1 sp1.

    It takes 10min to run this design example for 100usec. it will take me 9 days to run it for 135msec :-).

    Do you know a way how to speed up the simulation ? ??

    thanks

    Is it true that HMI interface is not yet supported in Quartus for Arria V and wouldn't be until 12.2 ???
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    same here, any progress guys?

    In my Arria V Kit, the local_init_done never gets asserted :( ... What I've tried?

    - I was told that HMI is disabled by default for Arria V ES http://www.altera.com/support/kdb/solutions/rd01302013_805.html

    I asked the local support to enable it, they advised me to put some option to turn on the HMI, into quartus.ini file but no help

    - Compiled with the latest 13.0, still ... doesn't work.

    If there's any workaround/issues, guys please post it, you can greatly save others' time!

    Thanks

    Jeff