DDR2 hard memory interface in ARRIA V

Any name with the AFI_ is the Avalon Interface from Altera, you can view it as a generic bus. The width of the bus varies with the speed / width you are running on the DDR2/3 interface. All that is configured for you thru MegaWizard (I am using the soft-core instead so maybe there's some difference). I suggest running the complete example design (can be conveniently generated by open the project file, and run the <vhdl/verilog>.tcl script) to visually help understand how the bus works.

Here are some links that maybe helpful to you:

Section 9 – MegaWizard Plug-In Manager Flow of the following: http://www.altera.com/literature/hb/external-memory/emi_plan.pdf

For an overview read this section: http://www.altera.com/literature/hb/external-memory/emi_intro.pdf

There is also a Stratix III/IV UniPHY tutorial: http://www.altera.com/literature/hb/external-memory/emi_tut_qdr.pdf

Here is all the documentation on the External Memory Interface Handbook: http://www.altera.com/literature/hb/external-memory/emi.pdf

Hope this helps