DDR2 hard memory interface in ARRIA V

Hi

I fixed it, but now I have different problem. the ddr2_example_design simulation doesn't work well.

I implemented a Hard memory interface (ddr2) for ARRIA V in the megawizard. And I wanted to activate the example design.

I run ddr2_example_design example design exactly as described in README.txt file

- open the Quartus project "generate_sim_example_design.qpf" and select Tools -> Tcl Scripts... -> generate_sim_vhdl_example_design.tcl and click "Run".The generated files will be found in the subdirectory "vhdl".

- To simulate the example design using Modelsim AE/SE:

1. Move into the directory ./verilog/mentor or ./vhdl/mentor

2. Start Modelsim and run the "run.do" script: in Modelsim, enter "do run.do".

In the Wave I don't see any action in the ddr2 signals(dq,dqs) its always in tri-state.

Attached the Wave screenshot.