DDR2 hard memory interface in ARRIA V

Hi,

Many thanks for your help. I've created a ddr2 ip with megawizard. like you said, it generate an example "ddr2_example_design".

I run the <vhdl/verilog>.tcl script , the project was compailed and I can see Waves.

some of the signals are RED (unknown state) : init_done,cal_success,cal_fail,status_fail...

in the model sim transcript window I see an error :ERROR: Invalid arc in, fsm:AVL_FSM, state:AVL_IDLE

# Instance: ddr2_example_sim.e0.if0.p0.ddr2_example_sim_e0_if0_p0_ddr2_example_sim_e0_if0_p0_acv_hard_memphy_umemphy_arriav_mem_phy_hphy_inst_6080.inst.<protected>.<protected>

# Time: 17867500

# ERROR: Invalid arc in, fsm:AVL_FSM, state:AVL_IDLE

# Instance: ddr2_example_sim.e0.if0.p0.ddr2_example_sim_e0_if0_p0_ddr2_example_sim_e0_if0_p0_acv_hard_memphy_umemphy_arriav_mem_phy_hphy_inst_6080.inst.<protected>.<protected>

# Time: 17880000

Do you know what is this error?

Thanks