DCLK and DATA0 connected to LVDS output instead of floating

I aggree to your considerations in so far, as I don't expect problems when connecting DCLK and DATA0 to a LVDS level logic signal during user mode. I didn't se a specification of the Cyclone II ST input buffer, so I can't say, if the LVDS signal will possibly cross the threshold levels during operation and if the hysteresis is larger than the maximum LVDS swing.

I also keep my opinion, that you can't derive conclusions about the behaviour of single ended inputs connected to in-between (LVDS) logic levels from the datasheet. But I must admit, it's more a theretical discussion about what can be said for sure.

P.S.: There should be simple option to "disconnect" the signals based on the state of CONFIG_DONE.

This could be tricky indeed.

I didn't find the hysteresis specifications for DClk and Data0 in the Cyclone II data sheet. I have the feeling that the LVDS levels applied after configuration could stay in the undefined zone. So without more information from Altera about the Schmitt Trigger hysteresis we don't know whether it will always work. Maybe the Ibis models could be of help? (if they are also given for Dclk and Data0)

One more observation is that at the end of the configuration of FPGAremote this may possibly start sending data on the LVDS outputs before you can tristate the TTL outputs on FPGA main, possibly disrupting the configuration.

Why not use 2 more wires between FPGAmain and FPGAremote?

Or use LVCMOS differential signalling instead of LVDS (saving 2 pins on FPGAmain as well)?

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There's no way than trying it yourself!

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Generally, it's simply good engineering praxis to avoid floating inputs. Floating input will at least cause additional current consumption, because the respective CMOS input buffers are possibly floating through their linear range. At worst case, very high frequent self oscillations can be brought up, causing excessive supply currents and interferences.

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Of course I can try it myself, but that doesn't mean that I get a statistically relevant result, which is why an answer with more insight might give me a bit more confidence about the risks I'm running.

As to floating, strictly speaking I don't keep them floating, I fix them to a narrow range (specifically the range of the LVDS signals), which should keep them from floating and in theory, this should be within spec of a Schmitt Trigger input.

The reason I want to implement it like this is that I have a remote unit which I want to program (re)using some of the wires to it which are normally used for LVDS dataexchange.

This means that I have an FPGAmain on my mainboard from which three wires (plus power) are running to the FPGAremote unit.

The FPGAmain will have one LVDS inputpair which I connect to two separate TTL outputs also on FPGAmain. Both lines are connected to DCLK and DATA0 on FPGAremote in addition to some LVDS outputpair on FPGAremote. There is one line from FPGAmain (TTL output) which is connected to nCONFIG on FPGAremote.

During startup FPGAmain is programmed using active mode via a flashrom.

Then FPGAmain will manipulate DCLK/DATA0/nCONFIG to FPGAremote using TTL levels to program it, after which FPGAmain will tri-state the drivers on the TTL-outputs for DCLK and DATA0 to FPGAremote, and subsequently will FPGAremote (after startup) use LVDS on that same signalpair to communicate to the corresponding LVDS inputpair on FPGAmain.

My assumption was that it might work because the inputs strictly aren't floating anymore and therefore should not pickup stray signals, and the fact that they're Schmitt Triggered should keep them from oscillating wildly because the LVDS levels do not hover around the Schmitt Trigger levels.

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Strictly speaking, the questioned circuit is violating the requirement of keeping the input either high or low.

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You don't have to keep Dclk And Data0 at either a logic high or a logic low indefinitely, they may toggle. We use the same signals for both configuring and controlling the FPGA, by connecting both Dclk and Data0 to an IO pin as well.

Seriously, noone can predict what's exactly happening with your circuit. Strictly speaking, the questioned circuit is violating the requirement of keeping the input either high or low. So I would avoid it. I guess however, that you have a reasonable motivation for the attempt. There's no way than trying it yourself! Furthermore, for obvious reasons you can be rather sure to get no satifying answer from Altera about unsupported features and device operation beyond the specified conditions.

Generally, it's simply good engineering praxis to avoid floating inputs. Floating input will at least cause additional current consumption, because the respective CMOS input buffers are possibly floating through their linear range. At worst case, very high frequent self oscillations can be brought up, causing excessive supply currents and interferences.

If you are using passive configuration mode you are driving Dclk and Data0 with a LVTTL signal during configuration, so where does the LVDS come in?

LVDS is not a LVTTL signal and although there is a schmitt-trigger input the LVDS level may fall in the intermediate zone.