DCLK and DATA0 connected to LVDS output instead of floating

Seriously, noone can predict what's exactly happening with your circuit. Strictly speaking, the questioned circuit is violating the requirement of keeping the input either high or low. So I would avoid it. I guess however, that you have a reasonable motivation for the attempt. There's no way than trying it yourself! Furthermore, for obvious reasons you can be rather sure to get no satifying answer from Altera about unsupported features and device operation beyond the specified conditions.

Generally, it's simply good engineering praxis to avoid floating inputs. Floating input will at least cause additional current consumption, because the respective CMOS input buffers are possibly floating through their linear range. At worst case, very high frequent self oscillations can be brought up, causing excessive supply currents and interferences.