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Altera_Forum
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16 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I aggree to your considerations in so far, as I don't expect problems when connecting DCLK and DATA0 to a LVDS level logic signal during user mode. I didn't se a specification of the Cyclone II ST input buffer, so I can't say, if the LVDS signal will possibly cross the threshold levels during operation and if the hysteresis is larger than the maximum LVDS swing.

I also keep my opinion, that you can't derive conclusions about the behaviour of single ended inputs connected to in-between (LVDS) logic levels from the datasheet. But I must admit, it's more a theretical discussion about what can be said for sure.

P.S.: There should be simple option to "disconnect" the signals based on the state of CONFIG_DONE.