Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

This could be tricky indeed.

I didn't find the hysteresis specifications for DClk and Data0 in the Cyclone II data sheet. I have the feeling that the LVDS levels applied after configuration could stay in the undefined zone. So without more information from Altera about the Schmitt Trigger hysteresis we don't know whether it will always work. Maybe the Ibis models could be of help? (if they are also given for Dclk and Data0)

One more observation is that at the end of the configuration of FPGAremote this may possibly start sending data on the LVDS outputs before you can tristate the TTL outputs on FPGA main, possibly disrupting the configuration.

Why not use 2 more wires between FPGAmain and FPGAremote?

Or use LVCMOS differential signalling instead of LVDS (saving 2 pins on FPGAmain as well)?