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Altera_Forum
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15 years ago

DCLK and DATA0 connected to LVDS output instead of floating

The Cyclone II handbook says that after programming, the DCLK and DATA0 inputs should not be left floating and should therefore be connected to a logic high or low. However, it also states that th...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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Strictly speaking, the questioned circuit is violating the requirement of keeping the input either high or low.

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You don't have to keep Dclk And Data0 at either a logic high or a logic low indefinitely, they may toggle. We use the same signals for both configuring and controlling the FPGA, by connecting both Dclk and Data0 to an IO pin as well.