DC-Coupling LVDS Tx to PCML Rx (Cyclone IV GX)

Question

I want to use a Cyclone IV transceiver input to receive a LVDS signal (about 800Mbps over 50cm cable). I need to use DC-coupling as the signal is not DC balanced.

Because of the Vcm requirement of the transceiver PCML input (0.82V) which conflicts with Vcm of the LVDS signal (about 1.2V), the interfacing is not trivial.

Does anybody know an IC that could be used for IO standard translation or has another clever idea?

Regards,

Thomas

www.entner-electronics.com

(Home of EEBlaster)

altera_forum · Answer

1. Why not use the Cyclone IV LVDS receiver SERDES block?

From the handbook: "LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx"

2. Assuming you cannot use an LVDS SERDES ...

Since the LVDS common mode is higher than the FPGA common-mode voltage, I suspect you could create a resistive divider that works ...

TI have a range of interfacing app notes ...

http://www.ti.com.cn/cn/lit/an/scaa062/scaa062.pdf

Look at Figure 13, which uses the following 1.5Gbps device

http://www.ti.com/product/sn65cml100

I did not check that the Vcm was compatible with the FPGA though.

Micrel also has a range of "Any Differential" translators, so you just need to find a CML output with a compatible Vcm.

http://www.micrel.com/index.php/en/products/clock-timing/clock-data-distribution/level-translators.html

http://www.micrel.com/index.php/en/products/clock-timing/clock-data-distribution/receivers-buffer-drivers.html

You understand of course that a transceiver is NOT a replacement for an LVDS receiver right? The clock-and-data recovery (CDR) unit in the transceiver will need to be forced into lock-to-reference mode, since it will not be able to operate in lock-to-data mode, since you do not have enough data transitions.

Cheers,

Dave

altera_forum · Answer

Hi Dave,

Thanks for your very informative response.

We cannot use regular LVDS pins for "historic" reasons, it is a small revision of an existing design. The 2.5V banks are all fully used. In fact, we need 6 channels in total, 4 are realized with regular LVDS pins and 2 by transceivers. The LVDS streams have embedded clocks with a guaranteed transition every 12 clocks.

The further explain: The design is already working. We did originally connect the LVDS signal directly to the transceiver inputs, however we had quite some problems with transmission errors. Then we got aware of this small footnote "LVDS only supported with 0.82 Vcm" and pulled down the Vcm by adding 1.3kOhm resistors to both lines of the pair as a hot-fix. This pulled the Vcm down to about 0.82V with our typical transmitter. This improved the link stability a lot. However we have sometimes still intermittent problems with errors (very random, even the same system sometimes show no problems for hours, then on the next day it produces a lot of errors, cause unclear, just a few suspects...). So we want to solve this Vcm thing in a cleaner way. We also want to improve the clock network as the second concern we have is that the problems are introduced by input clock jitter.

But back to the topic:

The SN65CML100 you suggested appears to support only termination voltages down to 1.8V. But at Micrel I found the SY54016AR (http://www.micrel.com/_pdf/hbw/sy54016ar.pdf) which looks good as it supports 2.5V/1.8V and 1.2V. But when looking further at the Altera documentation to find out if 1.2V would do instead of 1.5V, I realized that with CML it is assumed that both sides have termination resistors to Vcco (see figure 5a in above mentioned datasheet on page 11) while the transceivers (PCML) terminate to 0.82V. So I think when I connect the SY54016AR (with Vcco of 1.2V) to the FGPA (either with external termination to 1.2V or using the internal termination of the FPGA), I will not achieve this required Vcm of 0.82V +/- 10%.

So when thinking about this I think only AC-coupling is supported except for other transceivers outputs (PCML1.5/1.4) or (non-existing?) LVDS outputs with Vcm = 0.82V. In fact this is also what Table 1-2 is saying in http://www.altera.com/literature/hb/cyclone-iv/cyiv-52001.pdf.

Hmm, I guess I should not look for a CML output device but for something else differential with a Vcm of 0.82V?

Any thoughts?

Thanks,

Thomas

www.entner-electronics.com

(Home of EEBlaster)

altera_forum · Answer

--- Quote Start ---

The 2.5V banks are all fully used

--- Quote End ---

I vaguely recall that the receiver inputs are powered from VCCPD and in many cases LVDS can be received on any clock pin (don't hold me to that ...). The clock inputs will not have a SERDES block, but you could investigate whether a clock pin and fabric SERDES is a work-around for the couple of signals you need.

--- Quote Start ---

The LVDS streams have embedded clocks with a guaranteed transition every 12 clocks.

--- Quote End ---

Did you try an AC-coupled link? (Your comments above imply you only tested DC-coupled links, with a modified Vcm)

--- Quote Start ---

Any thoughts?

--- Quote End ---

I'll have a think about it some more.

I can think of one way that would work. 800Mbps is slow compared to transceiver rates. Since transceivers come in pairs, and you only want the RX, you could use the TX and an external high-speed XOR gate. The inputs to the XOR gate would be your signal and the transceiver TX. The XOR output would be AC-coupled to the receiver. The TX would output a PRBS pattern at say 4x the data rate (3.2Gbps). The output of the XOR is then modulated, allowing the RX signal to use the clock-and-data recovery (CDR) lock-to-data mode. The receive logic would then XOR the receiver output with the PRBS signal (appropriately delayed). The result will be a 4x over-sampled version of your receive signal. I'm currently using the XOR modulation technique to AC-couple 5Gbps and 10Gbps signals with a negative common-mode voltage onto an FPGA.

Cheers,

Dave

altera_forum · Answer

--- Quote Start ---

I think when I connect the SY54016AR (with Vcco of 1.2V) to the FGPA (either with external termination to 1.2V or using the internal termination of the FPGA), I will not achieve this required Vcm of 0.82V +/- 10%.

--- Quote End ---

If you can find a part with Vtt = 1.2V and Vpp = 0.8V, then this would produce Vcm = 1.2V - 0.8V/2 = 0.8V, which is within 10% of Vcm.

For example, the AD9956 AgileRF has a CML/PECL output driver that does not include resistors. On that part you can program the constant current, so with a 50-ohm termination at the FPGA, you could program an output current of (1.2V - 0.82V)/50-ohm = 7.6mA, and have the correct Vcm. I realize that this Analog Devices part is not suitable for your application, but it does show you that parts with programmable output voltage swing exist, and now you just have to find one :)

Cheers,

Dave

altera_forum · Answer

--- Quote Start ---

I vaguely recall that the receiver inputs are powered from VCCPD and in many cases LVDS can be received on any clock pin (don't hold me to that ...). The clock inputs will not have a SERDES block, but you could investigate whether a clock pin and fabric SERDES is a work-around for the couple of signals you need.

--- Quote End ---

Sorry, also all clock inputs already in use... The design is really big with a lot of clocks and I/O (DDR2, HDMI, PCIe, 3G-SDI, ...)

--- Quote Start ---

Did you try an AC-coupled link? (Your comments above imply you only tested DC-coupled links, with a modified Vcm)

--- Quote End ---

Our signal is not DC-balanced. I am considering to change to encoding of the signal to a DC-balanced format (we have control over the transmitting side, but some thoughts regarding backwards compatibility would be necessary...)

--- Quote Start ---

I can think of one way that would work. 800Mbps is slow compared to transceiver rates. Since transceivers come in pairs, and you only want the RX, you could use the TX and an external high-speed XOR gate. The inputs to the XOR gate would be your signal and the transceiver TX. The XOR output would be AC-coupled to the receiver. The TX would output a PRBS pattern at say 4x the data rate (3.2Gbps). The output of the XOR is then modulated, allowing the RX signal to use the clock-and-data recovery (CDR) lock-to-data mode. The receive logic would then XOR the receiver output with the PRBS signal (appropriately delayed). The result will be a 4x over-sampled version of your receive signal. I'm currently using the XOR modulation technique to AC-couple 5Gbps and 10Gbps signals with a negative common-mode voltage onto an FPGA.

--- Quote End ---

Sounds quite clever but also complex. In our case we could change the transmitter encoding as stated above.

--- Quote Start ---

If you can find a part with Vtt = 1.2V and Vpp = 0.8V, then this would produce Vcm = 1.2V - 0.8V/2 = 0.8V, which is within 10% of Vcm.

--- Quote End ---

True (but have not found any yet). I am also considering to use a LVDS to LVDS redriver and voltage dividers at the output (all close to the FPGA). This would give us a regular LVDS link over the cable and a controlable situation between redriver and FPGA.

Additionally we could also foresee capacitors for AC-coupling as mounting option instead of the redriver stuff.

Thanks,

Thomas

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DC-Coupling LVDS Tx to PCML Rx (Cyclone IV GX)

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